This invention relates to an information processing method and system in which a plurality of nodes operate synchronously by referring to flags.
The following two synchronizing mechanisms have been proposed to achieve synchronization among CPUs in a multiprocessor system:
(1) A synchronizing mechanism realized by allowing an individual CPU to occupy, at a certain instant in time, a common bus to which a plurality of CPUs are connected.
(2) A mechanism in which synchronization among the CPUs is achieved by using reserve flags.
The mechanism in (2) above has an instruction (referred to as a "load reserve", or "LR", instruction) for setting a reserve flag attendant upon a loading instruction for performing data readout, an instruction (referred to as a "store conditional", or "SC", instruction), which is one type of conditional store instruction, for checking the reserve flag prior to execution of a storing instruction, executing the storing instruction if the reserve flag is valid and then making the reserve flag invalid, and a function (referred to as a "store snoop", or "SS", function) with which the bus is monitored for making the reserve flag invalid if it is detected that another CPU has executed the storing instruction at an address identical with an address at which the LR instruction has been executed. The synchronizing mechanism is realized by using LR, SC and SS. Mechanism (2) aims at making the performance of a multiple-CPU system better than in mechanism (1) by not utilizing occupation of the bus.
However, when arbiters and nodes are connected via a connection path where information on the bus in each node cannot be snooped without being controlled by CPU, in a system of the type proposed in the above-mentioned CPU synchronizing techniques in which only address and control information accompanying a store instruction executed at each node is adopted as information necessary to implement synchronized operation, it is required that the synchronizing information always be sent to all nodes whenever the synchronizing information is received. Information is exchanged between nodes even in cases where CPUs are not being synchronized. As a consequence, there is unnecessary processing and traffic at arbiters and nodes, resulting in a decline in performance.